Verilog: Difference between revisions
Jump to navigation
Jump to search
Created page with "=Introduction= Dipping my toe into this now I own an fpga =Hello World= This is the first program <syntaxhighlight lang="v"> module and_gate ( // inputs input pmod_0, input pmod_1, // Outputs output led_0 ); assign led_0 = ~pmod_0 & ~pmod_1; endmodule </syntaxhighlight>" |
|||
| Line 2: | Line 2: | ||
Dipping my toe into this now I own an fpga | Dipping my toe into this now I own an fpga | ||
=Hello World= | =Hello World= | ||
This is the first program | This is the first program. There are two files to get it to work, a pcf file which defines things you use in the verilog file. Currently my understanding is it maps hardware to names which you can reference in the verilog file | ||
<syntaxhighlight lang="pcf"> | |||
#LED | |||
set_io led_0 41 | |||
#HEADER B I/O | |||
set_io -pullup yes pmod_0 23 | |||
set_io -pullup yes pmod_1 25 | |||
</syntaxhighlight> | |||
<syntaxhighlight lang="v"> | <syntaxhighlight lang="v"> | ||
module and_gate ( | module and_gate ( | ||
Revision as of 01:01, 21 January 2023
Introduction
Dipping my toe into this now I own an fpga
Hello World
This is the first program. There are two files to get it to work, a pcf file which defines things you use in the verilog file. Currently my understanding is it maps hardware to names which you can reference in the verilog file
#LED
set_io led_0 41
#HEADER B I/O
set_io -pullup yes pmod_0 23
set_io -pullup yes pmod_1 25module and_gate (
// inputs
input pmod_0,
input pmod_1,
// Outputs
output led_0
);
assign led_0 = ~pmod_0 & ~pmod_1;
endmodule